1. Field of the Invention
The present invention relates to the field of electronics. More specifically, the invention relates to a system and method for maintaining synchronization of information propagating through multiple, parallel pipelines.
2. Description of Related Art
Early microprocessors included circuitry arranged to process instructions in a serial manner along an instruction pipeline. To improve efficiency, more recent microprocessors (referred to as "pipelined microprocessors") have been designed to operate on several instructions simultaneously. This has been accomplished by overlapping operations performed during the "front-end" stages (e.g., the first few processing stages) of an instruction pipeline and operations performed during the "back-end" stage (e.g., the last few processing stages) of the instruction pipeline. In addition, selected processing stage(s) may be divided into substages for additional performance improvement as found in deeply pipelined microprocessors such as PENTIUM.RTM. PRO or PENTIUM.RTM. II which are produced by Intel Corporation of Santa Clara, Calif.
Until now, the need for multiple front-end pipelines has not surfaced. Currently, one reason for the lack of multiple front-end pipelines in microprocessors may be due to complexity or inapplicability with the architecture. If two or more parallel front-end pipelines are in operation (i.e., performing their own tasks but on the same instruction pointer "IP"), each corresponding stage of these front-end pipelines must match in validity and in information content. Thus, the front-end pipelines are required to maintain a synchronous relationship with each other.
If multiple front-end pipelines are implemented, the size of the logic structures supporting the front-end pipelines would likely prevent themselves from being placed in close proximity to each other. This would cause a delay in communicating events from one front-end pipeline to another. Examples of an "event" may include (i) a stall condition which halts the propagation of information (e.g., one or more instruction pointers "IPs") through these multiple front-end pipelines until the stall condition is deactivated or (ii) a flush condition which typically causes all information remaining in the front-end stages of a front-end pipeline to be invalidated. Since an event would be detected by one front-end pipeline before another, information in one front-end pipeline may become misaligned with corresponding information of the other front-end pipeline. Thus, these front-end pipelines would become asynchronous.
Hence, it would be advantageous to provide a system and method to maintain synchronization of the front-end stages of multiple front-end pipelines and to provide a synchronization scheme after the occurrence of an event which may cause the front-end pipelines to temporarily become asynchronous to each other.